The relentless expansion of CoWoS capacity, surging demand for HBM, and the rapid rise of Chiplet and 2.5D/3D packaging are not merely reflections of the AI boom. They point to a fundamental shift in the industry’s underlying logic: as the cost of advanced process nodes continues to climb and the dividends of scaling diminish, the path to higher chip performance is moving from “making transistors smaller” to “making system integration stronger.”
This is why more and more players are turning to multi‑die integration to strike a balance among performance, yield, and cost. Yet once advanced packaging entered volume production, the industry quickly realised that the real challenge is not just “how to stack, how to interconnect, or how to integrate,” but whether these architectures can be manufactured reliably. Mechanical stability after wafer thinning, warpage control after stacking, interface quality at finer interconnect pitches, and process compatibility among multiple materials all directly impact yield.
Three Pathways, One Common Threshold
The dominant trends in advanced packaging today are clear: larger package footprints, finer interconnect pitches, and newer material systems.
Larger footprints mean more chips and HBM dies are integrated into a single package; finer pitches are driving the industry from microbumps toward hybrid bonding; and the growing interest in glass substrates signals that traditional material platforms are approaching their limits. These may appear as three distinct paths, but at their core they all demand the same thing: higher precision, greater consistency, and more stable manufacturing capabilities.
Take hybrid bonding as an example. Success or failure often hinges not on the bonding step itself, but on the quality of front‑side surface preparation. Wafer surface flatness, roughness, particle control, and uniformity directly affect the integrity of the bonding interface.
Glass Substrates: The Real Hurdle Is Mass Production
Glass substrates are favoured for their low coefficient of thermal expansion, good mechanical stability, and low high‑frequency signal loss. Leading companies have been pushing validation and pilot production over the past two years, proving that glass is no longer just a “long‑term concept.”
However, material promise does not mean process issues have been solved. The TGV (through‑glass via) route, in particular, involves multiple critical steps – via formation, metal filling, surface planarisation, and high‑density redistribution – each of which places extreme demands on manufacturing capability. The true differentiator for glass substrates is not “whether they have a future,” but “who can make the process truly stable.”
Fundamental Processes Are Being Revalued
This is why competition in advanced packaging is increasingly gravitating toward precision machining. Whether it is ultra‑thin wafer grinding, surface preparation before hybrid bonding, or CMP planarisation after TGV filling for glass substrates, it all comes down to a few key questions: Can thickness be controlled consistently? Can surface flatness be ensured? Can defects be effectively contained?
In the past, processes like slicing, grinding, and polishing were often seen as basic manufacturing steps. But in the era of advanced packaging, they are becoming the gateway to viable volume production. Taking glass substrates as an example, CMP planarisation after TGV via filling imposes extremely tight requirements on dishing control. Siplus Semiconductor has already achieved dishing below 0.7 µm. The significance of such capability lies not in a single parameter, but in the manufacturing certainty it represents.
Advanced packaging is redefining not just packaging itself, but the centre of gravity in semiconductor manufacturing competition. In the end, what sets the upper limit is often not the most hyped concept, but the underlying process capabilities that can be executed reliably, consistently, and at scale.